As SRAM densities increase, it is becoming increasingly necessary to find alternative ways to obtain smaller SRAM cells. Stacked CMOS technology in which the P channel load is stacked on top of an N channel bulk transistor is being utilized for building 4 megabit memories and beyond. As the device geometry decreases, each cell therein becomes susceptible to soft radiation errors. As a result, it is imperative to utilize capacitors at the sensitive nodes to maintain charges which otherwise would be affected by exposure to soft radiation.
Under an existing stacked CMOS technology known as merged CMOS (MCMOS), a stacked CMOS latch is constructed with a single polysilicon layer overlying a bulk P type substrate. As a result, the source and drain regions of the underlying N channel transistor are not self-aligned to the gate electrode of the transistor. Further, the underlying bulk N channel transistor consumes Ca considerable amount of lateral area. Moreover, the gate oxide for both the N channel and P channel transistors comprises the same oxide layer and, as a result, must necessarily be of the same thickness for both transistors limiting the functionality of the transistors. Additionally, under the current art, there are no provisions for a stacked capacitor within the SRAM configuration.
Therefore, a need has arisen for a stacked CMOS cell which minimizes a real consumption and includes therein a stacked capacitive element to reduce susceptibility to soft radiation exposure. There also exists a need to provide independent gate oxides for the buried N channel transistor and overlying P channel transistor.